By Michael Keating Synopsys Fellow
This publication tackles head-on the demanding situations of electronic layout within the period of billion-transistor SoCs. It discusses primary layout thoughts in layout and coding required to supply strong, functionally right designs. It additionally presents particular thoughts for measuring and minimizing complexity in RTL code. ultimately, it discusses the tradeoff among RTL and high-level (C-based) layout and the way instruments and languages needs to growth to deal with the wishes of tomorrow’s SoC designs.
* offers an simply available advisor that permits readers to write down higher, extra verifiable code for advanced SoCs;
* Describes options for winning SoC layout, together with simplifying RTL layout, lowering complexity in control-dominated designs, decreasing complexity in facts course ruled designs, and simplifying interfaces;
* Discusses the tradeoff among RTL and high-level (C-based) layout and the way instruments and languages may still improve to fill destiny needs.
Early compliment for the easy paintings of SoC Design…
I have loved analyzing and reviewing the draft fabric for this ebook as Mike has constructed and subtle the content material. His readability and perception, received from operating with a number of mutual buyers and SOC designers, shines through.
Working in an the place profitable IP deployment is key to product good fortune, i discovered that this ebook addresses essentially what the fashion designer needs to concentrate on, from specification, partitioning and fresh interfacing via implementation to verification.
Highly prompt even if you're newly beginning out in SoC layout, otherwise you are an veteran weighed down with ever extra complicated method integration challenges.
David Flynn
Fellow, learn & improvement, ARM Ltd
Part-Time vacationing Professor in Electronics and desktop technology, college of Southampton, UK
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Extra resources for The Simple Art of SoC Design: Closing the Gap between RTL and ESL
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V of Frontmatter. M. 1007/978-1-4419-8586-6_2, © Synopsys, Inc. 2011 15 16 2 Simplifying RTL Design implementation is a complex task. As in any complex task, at some point it becomes easier to divide it into two separate tasks, and solve them separately. One of the byproducts of designing both the function and the implementation details simultaneously is that the code size tends to become quite large. Source code file sizes can often run into the tens of pages. The code tends to be structured to be friendly to the compilers not necessarily to the humans who read and debug the code.
In terms of RTL design, and in fact in any code based design, the key mechanism is encapsulation. We want to partition the design – and the code – so that each piece can be designed and analyzed separately from the other pieces. To the degree possible, we would like to encapsulate functionality, hide local information so that external pieces of the design don’t see it, and present a simple interface to the rest of the system. Even with today’s languages and tools, we can use encapsulation techniques to raise the level of abstraction above the traditional RTL level.
In addition, in RTL we describe both the function of the design and a great deal of the implementation details. For instance, we define the basic clocking structure and whether reset is synchronous or asynchronous. By the way we write the RTL we determine whether latches or flip-flops will be used. Historically, we have used code structure and coding style to develop code that is synthesis friendly, easy to achieve timing closure, and meets our power and gate count constraints. Clarity of the code has often been a secondary concern.