By Amir Zjajo
With the quick development of CMOS fabrication know-how, increasingly more signal-processing features are carried out within the electronic area for a lower price, reduce energy intake, greater yield, and better re-configurability. This has lately generated a very good call for for low-power, low-voltage A/D converters that may be learned in a mainstream deep-submicron CMOS know-how. in spite of the fact that, the discrepancies among lithography wavelengths and circuit characteristic sizes are expanding. reduce energy offer voltages considerably lessen noise margins and raise diversifications in method, machine and layout parameters. accordingly, it's progressively tougher to manage the fabrication approach accurately adequate to keep up uniformity. The inherent randomness of fabrics utilized in fabrication at nanoscopic scales signifies that functionality can be more and more variable, not just from die-to-die but additionally inside each one person die. Parametric variability may be compounded by means of degradation in nanoscale built-in circuits leading to instability of parameters over the years, finally resulting in the improvement of faults. technique edition can't be solved by means of enhancing production tolerances; variability has to be diminished via new equipment expertise or controlled via layout to ensure that scaling to proceed. equally, within-die functionality edition additionally imposes new demanding situations for try out methods.
In an try and deal with those concerns, Low-Power High-Resolution Analog-to-Digital Converters particularly concentrate on: i) bettering the facility potency for the high-speed, and occasional spurious spectral A/D conversion functionality by means of exploring the potential for low-voltage analog layout and calibration ideas, respectively, and ii) improvement of circuit strategies and algorithms to reinforce trying out and debugging capability to discover error dynamically, to isolate and confine faults, and to get well error regularly. The feasibility of the defined tools has been proven via measurements from the silicon prototypes fabricated in common 180nm, 90nm and 65nm CMOS technology.
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Additional resources for Low-Power High-Resolution Analog to Digital Converters: Design, Test and Calibration
Sample text
The conversion process is split into two steps as shown in Fig. 1. The first A/D sub-converter performs a coarse conversion of the input signal. A D/A converter is used to convert the digital output of the A/D sub-converter back into the analog domain. The output of the D/A converter is then subtracted from the analog input. The resulting signal, called the residue, is amplified and fed into a second A/D sub-converter which takes over the fine conversion to full resolution of the converter. The amplification between the two stages is not strictly necessary but is carried out nevertheless in most of the cases.
The high-speed capability of the amplifier is the result of the presence of only n-channel transistors in the signal path and of relatively small capacitance at the source of the cascode transistors. 30 2 Analog to Digital Conversion a VDD bias1 T7 T5 outn bias2 T3 bias3 T8 T6 outp T4 inp T2 T1 cmfb inn T3 VSS b VDD T9 bias1 bias1 T10 T7 bias2 bias2 T8 inp outn T5 T1 bias3 bias4 T3 T2 outp inn bias3 T6 cmfb T4 T11 cmfb VSS c VDD K:1 T6 T8 1:1 1:1 1:K T5 T4 T14 T7 T15 bias3 bias3 T9 outp outn inn T10 bias2 inp T2 T3 bias2 T12 KIB /2 T11 T17 T16 K:1 IB /2 bias1 T1 IB 1:K T13 IB /2 KIB /2 VSS Fig.
Normalizing the dissipated power P to the effective resolution ENOB and to the effective resolution bandwidth ERBW, the figure of merit, FoM ¼ P/(2ENOB Â 2 ERBW)) [107], is a measure for the required power per achieved resolution per conversion. Today, the state-of-the-art FoM for Nyquist A/D converters is around 1 pJ/conversion. 1 it can be seen that the flash architecture is (barely or) not used at all for accuracies above 6 bits due to the large intrinsic capacitance required. The most prominent drawback of flash A/D converter is the fact that the number of comparators grows exponentially with the number of bits.