By Grant Martin (auth.), Grant Martin, Henry Chang (eds.)
In 1998-99, on the sunrise of the SoC Revolution, we wrote Surviving the SOC Revolution: A advisor to Platform established Design. In that e-book, we fascinated by offering directions and most sensible practices to help engineers commencing to layout complicated System-on-Chip units (SoCs). Now, in 2003, dealing with the mid-point of that revolution, we think that it's time to concentrate on winning.
In this publication, Winning the SoC Revolution: studies in genuine Design, we assemble the easiest functional stories in how one can layout SoCs from the main complex layout teams, whereas environment the problems and strategies within the context of SoC layout methodologies. As an edited quantity, this booklet has contributions from the major layout homes who're successful in SoCs - Altera, ARM, IBM, Philips, TI, UC Berkeley, and Xilinx. those chapters current the various aspects of SoC layout - the platform established process, the best way to most sensible make the most of IP, Verification, FPGA materials in its place to ASICs, and subsequent iteration method expertise matters. We additionally comprise observations from Ron Wilson of CMP Media on top practices for SoC layout workforce collaboration. we are hoping that by using this e-book, you too, will win the SoC Revolution.
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Additional resources for Winning the SoC Revolution: Experiences in Real Design
Sample text
R. Goering, "Design reuse wi11 cut costs in half, study says", EE Times, September 28, 1998. Refers to study on IP return on investment by Michael Keating of Synopsys. R. This includes access to its various public documents, including the original Reuse THE HISTORY OF THE SOC REVOLUTION S. 9. 10. 11. 12. 13. 14. 15. 16. 17. IS. 19. 20. 21. 22. 23. 24. 25. 26. 19 Architecture document of 1997, as well as more recent documents supporting IP reuse released to the public domain. Michael Keating and Pierre Bricaud, Reuse Methodology Manual for System-on-a-Chip Designs, Kluwer, 1995 Wt • Edition), 1999 (2nd • Edition), 2002 (3 M• Edition).
Choudhury, A. Demir, E. Felt, E. Liu, E. Malavasi, A. Sangiovanni-VincenteIli and I. VassiIiou, A Top-Down, Constraint-Driven Design Methodology for Analog Integrated Circuits, Kluwer Academic Press, Boston, 1997. C. Lennard, C. and E. Granata, "The Meta-Methods: Managing Design Risk during IP Selection and Integration", The Intellectual Property System on Chip Conference, (Edinburgh, November 1999), p. 285. Chapter 3 NON-TECHNICAL ISSUES IN SOC DESIGN Ron Wilson EETimes Abstract: It is not just technical challenges that confront designers of complex SoC devices.
G. nlg .. k Controller Stlt. chln. vlc. ,. ,. Figure 2-6. Embedded Software Architecture Example In general, effective solutions to these issues revolve around careful architecting of ESW to layer it into a small amount of highly-optimized platform-dependent code, and a much larger amount of well-structured platform-independent code which can be more easily ported to new processors, real-time operation systems (RTOSs) and applications. This approach has been successful on a number of complex applications in the communications and automotive fields.