By Pinhong Chen
Because the characteristic dimension decreases in deep sub-micron designs, coupling capacitance turns into the dominant think about overall capacitance. The ensuing crosstalk noise could be liable for sign integrity matters and demanding timing version. characteristically, static timing research instruments have overlooked pass coupling results among wires altogether. more recent instruments easily approximate the coupling capacitance by means of a 2X Miller consider order to compute the worst case hold up. The latter procedure not just reduces hold up calculation accuracy, yet is also proven to underestimate the hold up in convinced eventualities. This publication describes actual yet conservative equipment for computing hold up version as a result of coupling. additionally, each one of these tools are computationally effective sufficient to be hired in a static timing research instrument for advanced built-in electronic circuits. to accomplish accuracy, a extra exact computation of the Miller issue is derived. to accomplish either computational potency and accuracy, quite a few mechanisms for pruning the quest house are designated, together with: -Spatial pruning - lowering aggressors to these in actual proximity, -Electrical pruning - lowering aggressors by means of electric energy, -Temporal pruning - lowering aggressors utilizing timing home windows, -Functional pruning - decreasing aggressors through Boolean sensible research.
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Extra info for Static Crosstalk-Noise Analysis: For Deep Sub-Micron Digital Designs (Solid Mechanics & Its Applications)
Example text
It may be combined with temporal pruning methods as described in Chapter 3 and 4 to give better accuracy. 34 7. STATIC CROSSTALK NOISE ANALYSIS FOR DSM DESIGNS Conclusion In this chapter, we have proposed a simple and accurate method to estimate the Miller factor for approximating a coupling circuit by a decoupled circuit. It is well-suited for coupling delay calculation in very deep submicron designs. An efficient Newton-Raphson method is proposed to find the Miller factors or effective capacitance.
2. We can estimate: so we have: It is not difficult to find real design values that make the L above greater than 1. 4. Suppose the aggressor net G is driven by a very strong AND gate, so its switching window is not affected by the weak aggressor net H. 4. 9ns. 1ns. This shows that we can have multiple convergence points depending on the initial switching window configuration. 1, and victim net and two aggressors and together create function where and are the fixed points. A repeated substitution procedure that replaces the argu- 46 STATIC CROSSTALK NOISE ANALYSIS FOR DSM DESIGNS ment with its output value can be used to converge the sequence.
Using Eq. 2), we can prove this monotonicity by induction as follows. 1 If in the initial two steps, for all quence, and and then forms a monotonically non-increasing seforms a monotonically non-decreasing sequence. Proof: The proof is by induction on the iteration number. The base case is clearly Assume that so is a non-decreasing function, so we have Also Therefore, 48 STATIC CROSSTALK NOISE ANALYSIS FOR DSM DESIGNS Similarly, the sequence can be proved symmetrically. 1 If the initial configuration starts from the maximum switching windows, forms a monotonically non-increasing sequence, and forms a monotonically non-decreasing sequence.