By Siva G. Narendra
Scaling transistors into the nanometer regime has led to a dramatic elevate in MOS leakage (i.e., off-state) present. Threshold voltages of transistors have scaled to take care of functionality at decreased strength offer voltages. Leakage present has develop into a massive section of the full energy intake, and in lots of scaled applied sciences leakage contributes 30-50% of the general strength intake below nominal working stipulations. Leakage is critical in a number of various contexts. for instance, in machine purposes, lively leakage strength (i.e., leakage strength whilst the processor is computing) is changing into major in comparison to switching energy. In battery operated platforms, standby leakage (i.e., leakage whilst the processor clock is became off) dominates as strength is drawn over lengthy idle sessions. elevated transistor leakages not just influence the general energy ate up through a CMOS method, but additionally decrease the margins to be had for layout as a result of robust courting among procedure edition and leakage energy. it's crucial for circuit and process designers to appreciate the parts of leakage, sensitivity of leakage to diversified layout parameters, and leakage mitigation suggestions in nanometer applied sciences. This publication presents an in-depth remedy of those concerns for researchers and product designers.
Read or Download Leakage in Nanometer CMOS Technologies PDF
Similar cad books
Digital Design and Modeling with VHDL and Synthesis
Electronic structures layout with VHDL and Synthesis offers an built-in method of electronic layout ideas, methods, and implementations to aid the reader layout even more advanced platforms inside of a shorter layout cycle. this can be comprehensive via introducing electronic layout techniques, VHDL coding, VHDL simulation, synthesis instructions, and methods jointly.
Low-Power High-Resolution Analog to Digital Converters: Design, Test and Calibration
With the short development of CMOS fabrication know-how, progressively more signal-processing features are applied within the electronic area for a cheaper price, reduce energy intake, larger yield, and better re-configurability. This has lately generated an exceptional call for for low-power, low-voltage A/D converters that may be discovered in a mainstream deep-submicron CMOS expertise.
CAD Tools and Algorithms for Product Design
Platforms to aid the continually shrinking product improvement cycles and the expanding caliber specifications want major improvements and new methods. during this ebook very important new instruments and algorithms for destiny product modeling structures are provided. it really is in accordance with a seminar on the foreign convention and examine middle for computing device technology, Schloß Dagstuhl, Germany, offered through the world over well-known specialists in CAD expertise.
- Dialogue and Technology: Art and Knowledge (Human-centred Systems)
- Programming Many-Core Chips
- CAD mit CATIA® V5: Handbuch mit praktischen Konstruktionsbeispielen aus dem Bereich Fahrzeugtechnik (German Edition)
- Process Model for Control, 1st Edition
- Practical Grey-box Process Identification: Theory and Applications (Advances in Industrial Control)
- From Knowledge Intensive CAD to Knowledge Intensive Engineering: IFIP TC5 WG5.2. Fourth Workshop on Knowledge Intensive CAD May 22–24, 2000, Parma, Italy
Additional info for Leakage in Nanometer CMOS Technologies
Sample text
B=l tOE-t03 1 10 100 1000 10000 Time (ns) Figure 2-11. Transient behavior of leakage current convergence time constant in a 2 NMOS stack under different temperature and initial input conditions. 0 20 40 60 80 100 Vt - reduction (mV) Figure 2-12, Dependence of leakage convergence time constant of stack leakage on threshold voltage, temperature, and initial input conditions. T = SO^C 0 25 50 75 Vt rediiction(mV) Figure 2-13. Leakage current increase with threshold voltage reduction at the transistor and adder block levels.
Back to the simulated data, the time required for the leakage current in transistor stacks to converge to its final value is dictated by the rate of charging or discharging of the capacitance at the intermediate node by the sub-threshold drain current of Ml or M2. This time constant as shown in Figure 2-11 is, therefore, determined by drain-body junction and gateoverlap capacitances per unit width, the input conditions immediately before the stack transistors are turned OFF, and transistor sub-threshold leakage current, which depends strongly on temperature and Vf Therefore, the convergence rate of leakage current in transistor stacks increases rapidly with Vt reduction and temperature increase, as shown in Figure 2-11 and Figure 2-12.
These methods begin with the approach of sizing the local sleep devices to meet the same performance constraint. Keeping the sleep devices separate at the local level allows CAD algorithms to relax the performance constraint for local gates while meeting the global constraint. One new approach uses local sleep devices at the gate level without any clustering [18]. This method sizes the sleep transistors to meet a global delay requirement by taking up all of the available slack in the design. This means that the delay for many individual gates increases more than the global constraint, but the total worst-case delay meets the constraint.