By Kanupriya Gulati, Sunil P. Khatri (auth.)
Hardware Acceleration of EDA Algorithms: customized ICs, FPGAs and GPUs
Kanupriya Gulati
Sunil P. Khatri
This publication offers with the acceleration of EDA algorithms utilizing systems reminiscent of customized ICs, FPGAs and GPUs. generally utilized CAD algorithms are studied for strength acceleration on those structures. insurance comprises dialogue of stipulations less than which it really is premier to exploit one platform over one other, e.g., whilst an EDA challenge has a excessive measure of information parallelism, the GPU is usually the popular platform, while while the matter has extra regulate, an FPGA can be hottest. effects are offered for the acceleration of numerous CAD algorithms (fault simulation, fault desk iteration, version card review in SPICE, Monte Carlo dependent statistical static timing research, Boolean Satisfiability), demonstrating speedups as much as 800X in comparison to single-core implementatinos of those algorithms.
This e-book serves as a priceless consultant on how most sensible to leverage parallelism to speed up CAD algorithms. It additionally provides a technique to immediately extract SIMD parallelism from normal uniprocessor code which satisfies a suite of constraints. With this method, such uniprocessor code can instantly be switched over to GPU code, making an allowance for major acceleration. This strategy is especially helpful due to the fact that diverse GPUs have enormously various requisites, making the handbook new release of GPU code an unscalable proposition.
In specific, this book:
- Provides directions on no matter if to take advantage of customized ICs, GPUs or FPGAs whilst accelerating a given EDA set of rules, validating those feedback with a concrete instance (Boolean Satisfiability) carried out on some of these platforms;
- Demonstrates the acceleration of numerous renowned EDA algorithms on GPUs, with speedups as much as 800X;
- Helps the reader by way of proposing instance algorithms that may be utilized by the reader to figure out how most sensible to speed up their particular EDA set of rules;
- Discusses an automated method of generate GPU code, given general uniprocessor code which satisfies a collection of constraints;
- Serves as a beneficial reference for somebody attracted to exploring substitute systems for accelerating numerous EDA functions by way of harnessing the parallelism to be had in those structures.
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Additional info for Hardware Acceleration of EDA Algorithms: Custom ICs, FPGAs and GPUs
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Combining multiple ICs together for more computing power and using an array of FPGAs for emulation purposes are known techniques to enhance scalability. However, the extra hardware usually requires careful reimplementation of some critical portions of the design. Further, parallel connectivity standards (PCI, PCI-X, EMIF) often fall short when scalability and extensibility are taken into consideration. Scalability is hard to achieve in general and should be considered during the architectural and design phases of FPGA-based or custom IC-based algorithm acceleration efforts.
In comparison to FPGAs or custom ICs, using GPUs as accelerators incurs a significantly lower design turn-around time. General-purpose CPU programming has all the advantages of GPGPU programming and is a mature field. Several programming environments, debugging and profiling tools, and operating systems have been around for decades now. The vast amount of existing code libraries for CPU-based applications is an added advantage of system implementation on a general-purpose CPU. 6 Scalability In high-performance computing, scalability is an important issue.
CUDA supports integer and bitwise operations completely, including integer texture lookups. The limitations of CUDA are as follows: • CUDA uses a recursion-free, function-pointer-free subset of the C language, plus some simple extensions. However, a single process must run spread across multiple disjoint memory spaces, unlike other C language runtime environments. 30 3 GPU Architecture and the CUDA Programming Model • The double precision support has some deviations from the IEEE 754 standard.