By Shi-Yu Huang, Kwang-Ting (Tim) Cheng
Formal Equivalence Checking and layout Debugging covers significant issues in layout verification: common sense equivalence checking and layout debugging. the 1st a part of the booklet stories the layout difficulties that require common sense equivalence checking and describes the underlying applied sciences which are used to unravel them. a few novel methods to the issues of verifying layout revisions after in depth sequential variations equivalent to retiming are defined intimately.
the second one a part of the booklet offers an intensive survey of earlier and up to date literature on layout errors prognosis and layout errors correction. This half additionally offers an in-depth research of the algorithms utilized in common sense debugging software program courses, ErrorTracer and AutoFix, constructed by means of the authors.
From the Foreword:
`With the adoption of the static sign-off method of verifying circuit implementations the application-specific built-in circuit (ASIC) will adventure the 1st radical methodological revolution because the adoption of common sense synthesis. Equivalence checking is among the serious parts of this methodological revolution. This publication is well timed for both the fashion designer looking to higher comprehend the mechanics of equivalence checking or for the CAD researcher who needs to enquire well-motivated learn difficulties comparable to equivalence checking of retimed designs or blunders prognosis in sequential circuits.'
Kurt Keutzer, collage of California, Berkeley
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Additional resources for Formal Equivalence Checking and Design Debugging
Sample text
Step 2 is a k-iteration loop that generates the first k input vectors. Each iteration identifies the combination of an input vector v and a state s that satisfies: • (v I s) as applied to the combinational portion of the product machine leads to the state s [k+ I ], and • s is in R[i]. Combinlttions satisfying this criterion are identified by pre-image computation as shown in the algorithm. If there are many such combinations, then only one will be selected and denoted as (v[i] I s[i]). 3 Speed-up Techniques In the entire verification algorithm, building the BDDs of the transition relation and performing the image-computation, are the two steps that may cause memory explosion.
Also, we use the array v to store the (k+ 1) vectors of the error trace, and the array s to store the states of the product machine in response to the error trace. Error_trace~eneration(T A R) T: transition relation ot'th~ product machine. A: primary output functions of the product machine. R: reachable states at each iteration of FSM traversal. P: a set of vectors in terms of BrnxBk. v: a distinguishing sequence to be generated. s: a sequence of states to which the error trace will bring the machine.
Fig. 2 Pruning the miter by finding a permissible pair. in the target pair are connected to an exclusive-OR gate. The output of this gate, denoted as f, further replaces the first signal a I. 1. Substitution-Based Algorithms 43 that if signalf stuck-at-O fault is untestable, then it is safe to replace al by signal a2 without changing the functions of 01 and the miter's output g. If a candidate pair (aI, a2) is found indeed permissible, the first signal al is replaced by the second signal a2 to simplify the miter as shown in Fig.