By Benoit Nadeau-Dostie
Layout for AT-Speed try, prognosis and size is the 1st booklet to supply functional and confirmed design-for-testability (DFT) recommendations to chip and process layout engineers, attempt engineers and product managers on the silicon point in addition to on the board and structures degrees. Designers will see how the implementation of embedded try out allows simplification of silicon debug and process bring-up. try engineers will confirm how embedded attempt presents an effective point of at-speed attempt, prognosis and size with out exceeding the functions in their apparatus. Product managers will find out how the time, assets and prices linked to attempt improvement, manufacture fee and lifecycle upkeep in their items will be considerably lowered through designing embedded attempt within the product. A whole layout circulation and research of the influence of embedded attempt on a layout makes this publication a `must learn' earlier than any DFT is tried.
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Additional info for Design for AT-Speed Test, Diagnosis and Measurement (FRONTIERS IN ELECTRONIC TESTING Volume 15)
Sample text
MemBIST-IC Approach To solve this problem, Logic Vision’s memory BIST approach requires that only one data line be routed to each embedded memory, regardless of the memory’s data width. This approach is referred to as a serial memory BIST, because the data values for each test pattern are provided serially to the memory. Figure 2-7 on page 40 shows this approach. The serial memory BIST approach involves using the memory itself to shift the incoming data bits across the data width of the memory.
Another issue that must be addressed by any solution is the testability of the logic surrounding the legacy cores. It is very difficult to propagate faults through untestable cores. Core outputs must be controllable and inputs must provide observation for the logic that drives the core. Logic Vision’s solution provides automatic generation of a configurable collar for isolation and access of a core. This feature supports hard, firm, and soft cores, provides dedicated isolation and access on a per-pin basis, and allows observation and control of the surrounding logic.
Asynchronous sets and resets. These signals must be disabled during BIST. Typically, only one flip-flop should be asynchronously reset per clock domain. All other flip-flops can be reset synchronously from the asynchronously reset flip-flop. The fault coverage loss is minimal and ATPG patterns, not reusable in the system, can be used to test the asynchronous sets and resets that are used. Internal tri-state bus drivers. Tri-state buses must be replaced with multiplexers whenever possible. If tri-state buses cannot be avoided, the enable signals of bus drivers must be uniquely decoded.