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SystemC 5. Impulse C 6. C2Verilog40 7. Mitrion C38 8. Handel-C 9. SpecC38 10. Napa C38 • Input interms of behavioral models written in C • Output interms of gate-level implementations • Output format interms of standard cells and programmable logic arrays or programmable logic devices • Accelerated design cycle, efficient designs • Maps behavioral level specification of hardware to a register transfer level description • Focus on concurrent processes, message passing, explicit instantiation of procedures, and templates • A compiler for simple hardware description language.

These days, systems may require a half-dozen or more clock signals, each at a different frequency [45]. The modern SoCs with Megahertz clock, suffers from large jitter due to variable transmission latency. Phase-locked loops (PLL) derive accurate sample clocks by jitter filtering. The digital implementation of phase detector, loop filter, and clock dividers is straightforward, whereas a digital substitute for analog VCOs is a challenging problem [46]. Therefore the former is preferred in most of the implementations.

3 SoC Buses In System-on-a-Chip (SoC), the bus architecture plays a vital role to achieve the shorter propagation delay. The conventional buses such as USB, FireWire, Ethernet, USART, SPI are still being used, but suffers severely in the multiprocessor environment owing to their global arbitration mechanism. This further leads to the problems such as congestion, leading to lowered bandwidth and higher latencies not acceptable in systems where deterministic timing is crucial [18]. The AMBA architecture from ARM has been widely adopted in the SoC paradigm due to its various verification attributes such as hierarchy of physical interconnect, unambiguous protocols and growing body of testbench and formal verification infrastructure [20].