By E. Macii
Energy intake is a key trouble in lots of high-speed and high-data-rate digital structures this present day, starting from cellular telecom to transportable and computer computing platforms, specially while relocating to nanometer applied sciences. Ultra Low-Power Electronics and layout deals to the reader the original chance of getting access to in a simple and built-in style a mixture of educational fabric and complicated examine effects, contributed by way of major scientists from academia and undefined, protecting the main scorching and up to date concerns within the box of the layout of extremely low-power units, platforms and functions.
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Sample text
Selected Topics in Quantum Electronics 3. [3] Y. Cao, T. Sato, D. Sylvester, M. Orchansky, and C. Hu: 2000, ‘New Paradigm of Predictive MOSFET and Interconnect Modeling for Early Circuit Design’. In: Proc. Custom Integrated Circuit Conference. [4] S. : 2002, ‘Integrated detectors for embedded optical interconnections on electrical boards, modules and integrated circuits’. IEEE J. Sel. Topics in Quantum Electronics 8. [5] A. 5-Gb/s directly modulated tunable VCSEL’. IEEE Phot. Tech. Lett. 15. [6] M.
De, Design and Optimization of DualThreshold Circuits for Low-Voltage Low-Power Applications, IEEE Transactions on Very Large Scale Integration (VLSI), Vol. 7, No. 1, March 1999, pp. 16-24. [25] N. Sirisantana, K. Roy, Low-Power Design Using Multiple Channel Lengths and Oxide Thicknesses, IEEE Design & Test of Computers, January-February 2004, pp. 56-63. [26] K. Nose, T. Sakurai, Optimization of VDD and VTH for Low-Power and High-Speed Applications, Proceedings of the Asia and South Pacific Design Automation Conference 2000, pp.
Recently, it has also been proposed to achieve modifications in Vth by modifying transistor length or gate oxide thickness Tox [25]. Design-tool support for this technique is also rudimentary at best. While it is becoming established to design different modules of an IC with different Vth transistors, it is very challenging to do this on the level of individual transistors within a module. The primary reason is that the entire design flow must be able to handle cells with identical functionality and size, which differ in their electrical properties.