By Chunjie Duan
On- and Off-Chip Crosstalk Avoidance in VLSI Design
Chunjie Duan, Brock J. LaMeres and Sunil P. Khatri
Deep Submicron (DSM) techniques current many demanding situations to large Scale Integration (VLSI) circuit designers. one of many maximum demanding situations is inter-wire crosstalk inside of on- and off-chip bus strains. Capacitive crosstalk in on-chip busses turns into major with shrinking characteristic sizes of VLSI fabrication methods, whereas inductive cross-talk turns into an issue for busses with excessive off-chip facts move charges. The presence of crosstalk vastly limits the rate and raises the facility intake of an IC design.
This ebook offers techniques to prevent crosstalk in either on-chip in addition to off-chip busses. those techniques permit the consumer to alternate off the measure of crosstalk mitigation opposed to the linked implementation overheads. during this manner, a continuum of strategies is gifted, which support increase the rate and gear intake of the bus interconnect. those concepts encode information earlier than transmission over the bus to prevent convinced bad crosstalk stipulations and thereby increase the bus velocity and/or strength intake. specifically, this book:
- Presents novel how one can mix chip and package deal layout, lowering off-chip crosstalk in order that VLSI structures may be designed to function considerably faster;
- Provides a entire set of bus crosstalk cancellation suggestions, either memoryless and memory-based;
- Provides strategies to layout tremendous effective formats for crosstalk cancellation;
- Provides crosstalk cancellation methods for multi-valued busses;
- Offers a battery of techniques for a VLSI dressmaker to exploit, reckoning on the quantity of crosstalk their layout can tolerate, and the volume of region overhead they could find the money for.
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Example text
M > n. This is not always the case, however, as we will show in Chap. 6. The additional wires used for a coded bus are considered as area overhead because of the additional routing space these wires occupy. The overhead percentage is defined as in Eq. 29. Note that the area of the encoder and decoder (CODEC) circuit are not included in the calculation of the area overhead. Instead, the encoder and decoder size are evaluated separately. This allows us to evaluate the code efficiency and CODEC efficiency separately.
The clique type, Qtype , is “01” when 01 is present in the last two bits of the codewords in the set. Conversely, Qtype = 10 when 01 is present in the boundary. T (n) is the cardinality of Qn and Txy (0) is the number of vectors ending with xy in Qn . 3 is of “10” type and therefore does not contain vectors with dn dn+1 = 10. 3, we can produce cliques of arbitrary bus sizes. The procedure, however, does not necessarily yield a 2C-free clique with maximal cardinality. As we pointed out earlier, vectors Vn,00 ·1 and V01 ·1 are not compatible, neither are Vn,11 · 0 and Vn,10 · 0.
Since no current flows through Vdd in output-high state, we know Ef , j ≡ 0. , Vj (t + ) = Vdd . Vj (t) is simplified as Vj hereafter. 4) where dVj, k = dVj − dVk . Now Eq. 8) 20 2 Preliminaries to On-Chip Crosstalk δj, k is the normalized relative voltage change of the kth line with respect to the jth line, and δj, k ∈ {0, ±1}. 9) + EjI where EjL = CL · Vdd · Vj and EjI = (2 − δj, j−1 − δj, j+1 )λCL · Vdd · Vj . 9 can be interpreted as the total energy to drive a line and it can be expressed as the sum of the energy to charge the substrate capacitor, EjL , and the energy to charge the inter-wire capacitors, EjI .