By Fei Yuan
CMOS Circuits for Passive instant Microsystems via Fei Yuan This ebook presents a entire therapy of the layout ideas and implementation of CMOS circuits and structures for passive instant microsystems. significant topics lined within the publication comprise: passive instant microsystems, radio-frequency strength harvest, facts encoding, modulators and demodulators, low-power precision voltage references, clock new release and calibration, and low-power analog-to-digital converters. This book’s contents function an exhaustive survey of lately released paintings during this quick evolving box, and are offered with an emphasis on either the layout ideas and in-depth comparability of the professionals and cons of the designs. This publication offers the cutting-edge of CMOS circuits for passive instant microsystems. it truly is a useful source for graduate scholars, IC layout engineers and researchers operating during this fast-evolving box. •Systematically offers CMOS circuit implementation of passive instant microsystems, delivering either theoretical history and useful implementation examples; •Provides in-depth comparability of the professionals and cons of alternative topologies of CMOS circuits for passive instant microsystems; •Focuses on highly-applied issues, equivalent to radio-frequency energy harvesting, voltage multipliers, ultra-low energy present and voltage references for passive instant microsystems, low-power ASK demodulators for passive instant microsystems, distant clock calibration of passive instant microsystems, and low-power analog-to-digital converters.
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Extra info for CMOS Circuits for Passive Wireless Microsystems
Example text
84) as VL 1 = VT 2 1+ Q2 k 2 Q1 Q2 + 1 2 . 87) that a large voltage gain of the step-up transformer matching network can be obtained by (i) boosting the mutual inductance M , (ii) lowering the series resistance of the primary winding, (iii) lowering the series resistance of the secondary winding, and (iv) increasing the self inductance of the secondary winding. There are two ways to increase the mutual inductance M : increase the coupling coefficient or increase the turn ratio. The former can only be achieved by using a stacked configuration while the latter requires a large number of the turns of the secondary winding.
C1 is charged by the input voltage. Note that without transistor M1B, the maximum voltage of V1 will only reach Vm − VT , where Vm is the amplitude of Vin and VT is the threshold voltage of MOSFETs. Since M2A is off, the gate voltage of M1B is at VDD and M1B is in the triode. As a result, V1,max = Vm − Vds1 ≈Vm . The drawback of the voltage loss of Dickson voltage multipliers is therefore removed. 5V and Iout = 10µA, the output voltage of a 4-stage Dickson voltage multiplier with static charge transfer switches is approximately 4 V.
Also, the large channel resistance of native MOSFETs deteriorates the performance. 11 [26]. It is ready to verify that once a load is connected between nodes 1 and 2, the current flowing through the load is always in the same direction. A key advantage of this voltage multiplier is the low voltage drop across switching MOSFETs. As a result, a large voltage exists at the output of the rectifying cell and is given by Vout,max = Vm − (VDS,n + VSD,p ). The modular configuration of Mandal-Sarpeshkar voltage multiplier offers the flexibility of adjusting the size of each stage to obtain optimal performance.