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Advanced Interconnects for ULSI Technology by Mikhail Baklanov, Paul S. Ho, Ehrenfried Zschech

By Mikhail Baklanov, Paul S. Ho, Ehrenfried Zschech

Discovering new fabrics for copper/low-k interconnects is necessary to the continued improvement of computing device chips. whereas copper/low-k interconnects have served good, making an allowance for the construction of extremely huge Scale Integration (ULSI) units which mix over one billion transistors onto a unmarried chip, the elevated resistance and RC-delay on the smaller scale has develop into a major factor affecting chip functionality.

Advanced Interconnects for ULSI Technology is devoted to the fabrics and techniques that may be compatible replacements. It covers a large diversity of issues, from actual rules to layout, fabrication, characterization, and alertness of latest fabrics for nano-interconnects, and discusses:

  • Interconnect capabilities, characterisations, electric homes and wiring specifications
  • Low-k fabrics: basics, advances and mechanical  homes
  • Conductive layers and limitations
  • Integration and reliability together with mechanical reliability, electromigration and electric breakdown
  • New ways together with 3D, optical, instant interchip, and carbon-based interconnects

Intended for postgraduate scholars and researchers, in academia and undefined, this ebook offers a serious evaluate of the permitting know-how on the middle of the long run improvement of laptop chips.

Chapter 1 Low?k fabrics: fresh Advances (pages 1–33): Geraud Dubois and Willi Volksen
Chapter 2 Ultra?Low?k via CVD: Deposition and Curing (pages 35–77): Vincent Jousseaume, Aziz Zenasni, Olivier Gourhant, Laurent Favennec and Mikhail R. Baklanov
Chapter three Plasma Processing of Low?k Dielectrics (pages 79–128): Hualiang Shi, Denis Shamiryan, Jean?Francois de Marneffe, Huai Huang, Paul S. Ho and Mikhail R. Baklanov
Chapter four rainy fresh purposes in Porous Low?k Patterning methods (pages 129–171): Quoc Toan Le, man Vereecke, Herbert Struyf, Els Kesters and Mikhail R. Baklanov
Chapter five Copper Electroplating for On?Chip Metallization (pages 173–191): Valery M. Dubin
Chapter 6 Diffusion limitations (pages 193–234): Michael Hecker and Rene Hubner
Chapter 7 method Integration of Interconnects (pages 235–265): Sridhar Balakrishnan, Ruth mind and Larry Zhao
Chapter eight Chemical Mechanical Planarization for Cu–Low?k Integration (pages 267–289): Gautam Banerjee
Chapter nine Scaling and Microstructure results on Electromigration Reliability for Cu Interconnects (pages 291–337): Chao?Kun Hu, Rene Hubner, Lijuan Zhang, Meike Hauschildt and Paul S. Ho
Chapter 10 Mechanical Reliability of Low?k Dielectrics (pages 339–367): Kris Vanstreels, Han Li and Joost J. Vlassak
Chapter eleven electric Breakdown in complicated Interconnect Dielectrics (pages 369–434): Ennis T. Ogawa and Oliver Aubel
Chapter 12 3D Interconnect know-how (pages 435–490): John U. Knickerbocker, Lay Wai Kong, Sven Niese, Alain Diebold and Ehrenfried Zschech
Chapter thirteen Carbon Nanotubes for Interconnects (pages 491–502): Mizuhisa Nihei, Motonobu Sato, Akio Kawabata, Shintaro Sato and Yuji Awano
Chapter 14 Optical Interconnects (pages 503–542): Wim Bogaerts
Chapter 15 instant Interchip Interconnects (pages 543–563): Takamaro Kikkawa

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Indd 15 12/20/2011 12:45:56 PM 16 Advanced Interconnects for ULSI Technology layer at the trench level [8, 123–125]. Although this approach limits plasma damage mainly to the via level (top and sidewall surfaces), it complicates the integration approach. g. polyarylenes or poly(arylene ethers), are deposited by spin-on techniques and the majority of organosilicate materials are prepared by PECVD, two distinctly different deposition tool sets would be required. Furthermore, the introduction of new interfaces, as mentioned previously for pore sealing using thin liners, may significantly affect interfacial adhesion.

1). Interestingly, the real IBM technology node/dielectric constant relationship differs significantly from the targets proposed by the NTRS in 1997. This shows the danger of predicting dielectric targets based solely on engineering designs when new materials are not readily available. The challenges in designing dielectric insulators that meet all the BEOL requirements (electrical, thermal and mechanical) have been the source of many publications over the last 15 years [1]. Among them, many excellent reviews have been published, addressing the different aspects of these dielectric materials: physical properties [7, 11–13], integration requirements and challenges [14, 15], characterization [9, 16–19] and chemistry [1].

5 after several days). This observation is in good agreement with an ellipsometric porosimetry (EP) study using water as an adsorbent, reporting that the in situ crystallized film’s hydrophilicity increases with aging [135]. 1) due to the additional porosity gained from internanocrystal packing voids [132]. 40 cm3 g−1 were measured by N2 adsorption experiments performed on bulk samples. While beneficial in terms of the dielectric constant, the presence of larger mesopores is not only of concern for practical applications but also affects the adhesive properties of these films, leading to failure during CMP [136].

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