By Douglas E. Ott
A Designer's consultant to VHDL Synthesis is meant for either layout engineers who are looking to use VHDL-based good judgment synthesis ASICs and for managers who have to achieve a pragmatic realizing of the problems concerned with utilizing this expertise. The emphasis is positioned extra on useful purposes of VHDL and synthesis according to real studies, instead of on a extra theoretical method of the language.
VHDL and good judgment synthesis instruments offer very robust functions for ASIC layout, yet also are very advanced and characterize a thorough departure from conventional layout tools. this case has made it tough to start in utilizing this know-how for either designers and administration, when you consider that an enormous studying attempt and `culture' switch is needed. A Designer's advisor to VHDL Synthesis has been written to aid layout engineers and different execs effectively make the transition to a layout method according to VHDL and log synthesis rather than the extra conventional schematic established method. whereas there are many texts at the VHDL language and its use in simulation, little has been written from a designer's point of view on the best way to use VHDL and good judgment synthesis to layout genuine ASIC platforms. the cloth during this publication relies on event received in effectively utilizing those thoughts for ASIC layout and is predicated seriously on life like examples to illustrate the rules concerned.
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Additional resources for A Designer’s Guide to VHDL Synthesis
For example, if you look at the general method of how digital systems are developed from Chapter 2, a block diagram is created identifying the inputs and outputs, the main functional blocks, and the interconnection between those blocks. The design of the major functions may in turn require a more detailed block diagram to assist both the final gate level logic design and the planning for logic simulation and test pattern generation. The VHDL language has been designed to support all of these types of operations, including partitioning and design hierarchy, in a straightforward manner.
Starting with the detailed block diagrams, the overall ASIC is roughly partitioned into sections oflogic that belong together, which form the basis for generating VHDL blocks called Entities. (As discussed further in Chapter 3, it is desirable to limit the size of these blocks to several thousand gates if possible due to considerations of both ASIC floorplanning and synthesis workstation performance, but this is simply a practical guideline that will most likely grow in the future). Each of these blocks will have inputs and outputs connected to other blocks in the ASIC, plus all of the internal functions within the block.
Figure 2-4 shows how the detailed design and simulation tasks for VHOL synthesis compare with the conventional approach. + Schematic Entry + Net1ist Generation + Gate Level Logic SimuJation I + VHDL Coding + RTL Level VHDL SimuJation i Logic Synthesis Figure 2-4 : Comparison of Detailed Design Flows Using the traditional system, you nonnally begin with the detailed block diagrams and for each logic function roughly sketch out the circuit details prior to drawing the schematics on your CAE system.